Such packaging for quartz or piezoelectric resonators of small dimensions are of two different kinds in the prior art. A first kind of packaging consists in metal cases, which are not always available in SMD (Surface Mounted Device) versions, and whose minimal size is limited by technology. A second kind of packaging consists in ceramic cases, which are SMD, but whose size is limited by the technology of production as well as the tolerances of manufacturing.
In view of the increasingly pressing request of the market, SMD packages that are smaller and offer stronger resistance to the higher temperatures of reflow soldering are required. The above cited types of metallic or ceramic cases do not allow to manufacture satisfying packaging for the small resonators that are needed.
Thus according to existing packaging technology, either the overall size of the packaging 1 will be unacceptably large, or else the inside of the packaging will be so close to the resonator edges, that there will be a considerable risk of loss due to the tolerances of manufacturing. For instance as shown in FIG. 1, for a resonator 6 having a length of about 1.5 mm and a width of about 0.65 mm, a ceramic package 1 according to the prior art presents an external length of at least 2 mm and external width of at least 1.2 mm. Since the thickness of the package walls 2 are about 0.2 mm, the cavity 3 inside has a length of 1.6 mm and a width of about 0.8 mm. With the traditional manufacturing techniques, dimensions may be obtained with a precision of about 0.12 mm. Consequently, the internal sides 5 of the package risk to be very close to the edges of the resonator 6 especially in the corner 7 where a connection traverses the package 1 to make contact with the outside. This connection inevitably causes some leakages 8 that may short-circuit the resonator electrodes (not represented). The other possibility, which consists in manufacturing wider packages, is not a satisfactory solution because of miniaturization issues.
Within the scope of the present invention, alternative solutions have been investigated, among which cases made of silicon on insulator as shown in FIG. 2. Use of silicon allows manufacturing most of the package or case 10, namely the base part 11 and the wall 12 with small and accurate manufacturing limits. This better dimensional tolerance results from the use of a semiconductor photolithographic process and an etching technique such as DRIE (Deep Reactive Ion Etching), where the inner corners are not rounded. Thus for given external dimensions of the package 10, thanks to the previous point, a larger cavity 13 may be obtained. This in turn improves the mounting conditions of the resonator 14 (schematically represented as a crystal) within the case.
In this context, as shown in FIG. 2, a case 10 has been developed comprising a base part 11 and a wall 12, which are both made of silicon. The base part 11 and the wall 12 are etched from a silicon wafer of the Silicon On Insulator (SOI) type. Such a wafer is actually formed of two silicon layers joined by an intermediate layer of silicon oxide. The silicon forming the layer out of which the base part is etched is preferably doped so as to render it conductive, while the silicon forming the layer out of which the wall is etched is preferably non doped so as to render it almost insulating. The silicon base part 11 includes two conductive vias 16a and 16b arranged to connect the inside piezoelectric resonator 14, for instance a crystal of quartz, to an outside circuit (not shown) through the base part 11. The conductive vias 16a and 16b are insulated from the rest of the base part 17 by a dielectric lining 18. Further, for the connection between the resonator 14 and the outside circuit, inner electrodes (20a and 20b) and outer electrodes (19a and 19b) are provided inside and outside case 10 respectively.
Even non doped silicon can conduct electricity considerably better than ceramic for instance. Accordingly, one problem with the silicon packaging shown in FIG. 2 is the considerable static capacity of the assembly formed by the case 10 and the resonator 14. As shown in FIG. 2 and schematically in FIG. 3, such a package design is equivalent to connecting several capacities C1, C2 and C3 in parallel with the crystal (i.e. the resonator). Consequently the overall static capacity of the assembly is drastically increased, which is harmful in the desired applications. Referring now to FIGS. 2 and 3, it can be seen that the total capacity between one via and the bulk of the base plate is:C4=C1+C2+C3Then the overall static capacity in parallel with the crystal is the following:CP=C4/2
The different capacities C1, C2, C3 are determined by the thickness of insulating material, i.e. dielectric. For instance if we consider an equivalent capacity C4 of 18 pF, a quick estimate of the static capacity Cp leads to a value of 9 pF which is about 15 times greater than the typical values obtained with ceramic packages.